Method for simulation of partial VLSI ASIC design

摘要

A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.