Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integration

摘要

Currently a monolithic self configuring test structure has been fabricated which achieves wafer scale integration levels through General Dynamics patented architecture, new technology and methodologies. The test structure uses a new double metal 3.0-micron GD/P:WSI CMOS technology. The device was not developed as a functional product, but rather as a test of the configuration manager, configuration management architecture and the new GD/P:WSI30G technology. The device consists of four quadrants of functionality clusters and configuration managers (CMs).