A case study of functional design using functional simulation and logic synthesis

摘要

Design time reduction to a half of what was previously required was achieved by a register-transfer-level (RTL) design procedure. The problems encountered in rule-based synthesis were identified through a detailed comparison of the manual logic design procedure with the rule-based logic synthesis procedure. A logic synthesizer using a rule base for local transformations was developed that is able to generate practical logic circuits, even if the RTL descriptions for the circuits are large. The synthesized logic circuits are influenced by the form of the RTL descriptions. The logic synthesizer must generate the good logic circuits, using the meaning of the macro function. The logic synthesizer, using the local optimization, cannot remove the redundancy of the deep if-clause-nesting without the circuit semantics. If there are rules that clear the gates to allow the signal to move forward, more satisfactory optimization will be realized.