IEEE International Conference on Computer-Aided Design, ICCAD-88. Digest of Technical Papers (IEEE Cat. No.88CH2657-5)

摘要

The following topics are dealt with: verification; statistical design techniques; switchbox routing; high-level synthesis; timing simulators; channel routing; multilevel synthesis; device simulation and modeling; CMOS matrix layout; finite-state-machine synthesis; algorithmic fault simulation techniques; global routing; fault simulation on high-performance computers ; power-bus current estimation; performance issues for VLSI; self-test and testable design techniques; multilevel simulation; processor architecture issues for CAD; analog layout parallel simulation techniques; circuit verification parametric issues and techniques in testing; switch-level simulation; ROM-based CMOS cell generation; test compaction and scheduling; frameworks for CAD; topological routing; automatic test pattern generation; circuit simulation; floorplannng; technology mapping and PLAs; analog circuit synthesis and optimization; placement; reconfiguration for yield enhancement; layout data structures; and analog layout. Abstracts of individual papers can be found under the relevant classification codes in this or other issues.