HPC GPS BASED AUTONOMOUSNAVIGATION SYSTEM FOR FUTUREGENERATIONS OF SATELLITES

摘要

This paper elaborates on the development of a space bornrnautonomous navigation system utilising the advancedrnGlobal Positioning System (GPS) and High PerformancernComputing (HPC) technology for future generations ofrnsatellite systems.rnGPS is a device integrated into the satellite system tornsense spacecraft trajectory and attitude, measure thernrelative distance between space vehicles, deliver preciserntime synchronisation to spacecraft electronics, and soundrnthe atmosphere. However, the advances in GPSrntechnology are not sychronised with the current capabilityrnof a standard spacecraft system to handle all thernmeasurements and provide on-board processing capacityrnto use these measurements for autonomous navigation.rnCurrent spacecraft systems provide very limited on-boardrncomputing capability, and therefore these satellites rely onrnother devices to provide information about the spacecraftrnposition such as star cameras and some times requirernground processing of data to give instructions onrnappropriate positions of the satellite.rnHPC systems consist of reconfigurable logic circuitsrnadded to a conventional processor to generate a powerfulrnsystem for handling intensive computing tasks.Reconfigurable Computing Technology (RCT) usingrnField Programmable Gate Arrays (FPGAs) represents arnflexible computing platform where both the hardware andrnthe software can be programmed on an application byrnapplication basis. This emerging technology is veryrnpromising for a lot of applications, especially satelliternsystems.rnThis paper investigates the deployment of HPC in therncontext of real-time reactive computer system on-boardrnthe spacecraft in conjunction with the GPS to implementrnthe autonomous navigation system. In particular, thernpaper introduces the use of a reconfigurable computer forrnposition and velocity computations of the spacecraftrnefficiently, with a focus on cost-effective implementationrnof precise orbit determination and control algorithms onrnFPGAs. Experimental testbeds for this research are alsornpresented.