SoC Memory Test Optimization using NXP MTR Solutions

摘要

Despite the current Moore's Law deceleration, the memory content of SoCs experienced a huge increase in the last decade, growing from 20% to more than 60% of the chip area on the average. Consequently, efficient testing of embedded memories is becoming exceedingly important. Memory Built in Self-Test (MBIST) modules are frequently embedded into SoCs to speed-up memory test to minimize the test cost. On the other hand, the addition of MBIST logic can increase the SoC die size and consequently its manufacture cost, especially if all memories are tested concurrently. Sequential MBIST modules (which test one memory at a time) can have smaller area but testing memories sequentially can result in an increase in test time. This paper proposes a methodology to balance memory test time vs. area overhead thus ensuring optimal memory test cost. It also presents some real-world case studies in which the application of such optimization methodology resulted in a meaningful reduction in the cumulative memory test cost of some recent NXP SoCs.