Design and Test of A Low-voltage Rail-to-rail op-amp with Constant Transconductance and SR

摘要

A low-voltage rail-to-rail op-amp with constant transconductance and slew rate is proposed. Input stage is achieved by a dummy NMOS and PMOS parallel input pairs, output stage is push-pull. The circuit obtains constant tansconductance and slew rate over the entire input common mode voltage range. The circuit design is realized in 0.18um CMOS technology and work in a 3.3V supply voltage. The circuit performance has been verified using HSPICE simulation. The simulation results show that the dc gain of the op-amp is 49dB, and the variation in transconductance is about 10%, and the variation in slew rate is changless.