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Teaching freshmen VHDL-based digital design

机译:教新生基于VHDL的数字设计

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Industry demand for highly-skilled digital VLSI and embedded systems engineers has made the teaching of design a challenging task for undergraduate educators. Increasingly challenging electronic design automation (EDA) environments call for a variety of skills in engineering graduates which necessitate not only industrial skills but also fundementals in basic science and digital design. These urgent needs are addressed by creating a digital logic design course taught at the freshman level that introduces students to VHDL design of digital VLSI systems while including core concepts. Critical thinking, logic synthesis and circuit innovation take priority over conventional analysis techniques. This case study includes example design projects that have been successfully implemented at The University of Akron.
机译:工业界对高技能的数字VLSI和嵌入式系统工程师的需求已使设计教学成为本科教育工作者的一项艰巨任务。越来越具有挑战性的电子设计自动化(EDA)环境要求工程专业的毕业生具备各种技能,这不仅需要工业技能,而且还需要基础科学和数字设计的基础知识。通过在新生阶段开设数字逻辑设计课程来满足这些紧急需求,该课程向学生介绍数字VLSI系统的VHDL设计,同时包括核心概念。批判性思维,逻辑综合和电路创新优先于常规分析技术。该案例研究包括在阿克伦大学成功实施的示例设计项目。

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