首页> 外文会议>International symposium on semiconductor manufacturing >A New LSI Manufacturing Scheme in the Large-Diameter Wafer Era for Super-Quick TAT Development and Volume Production
【24h】

A New LSI Manufacturing Scheme in the Large-Diameter Wafer Era for Super-Quick TAT Development and Volume Production

机译:大直径晶圆时代的新型LSI制造方案,用于超快速TAT开发和批量生产

获取原文
获取原文并翻译 | 示例

摘要

We describe a new LSI manufacturing scheme which features the compatibility of quick TAT development and volume production. It is composed of a main production line and extra paths of single-wafer processing. In the super-quick TAT runs, all of the batch process steps in the main line are replaced by single-wafer processing. The process compatibility enables us to smoothly transfer from development to volume production. We discuss implementation issues, and show experimental and simulation results to verify the effectiveness of this concept in the development of logic and memory products. This approach will reduce the cost for process development, and enhance the evolution of single-wafer processing equipment towards the large-diameter wafer era.
机译:我们描述了一种新的LSI制造方案,该方案具有快速TAT开发和批量生产的兼容性。它由一条主要生产线和单晶圆加工的额外路径组成。在超快速TAT运行中,主生产线中的所有批处理步骤均由单晶片处理代替。工艺兼容性使我们能够顺利地从开发过渡到批量生产。我们讨论实现问题,并显示实验和仿真结果,以验证该概念在逻辑和存储器产品开发中的有效性。这种方法将减少工艺开发的成本,并促进单晶片加工设备向大直径晶片时代的发展。

著录项

  • 来源
  • 会议地点 Austin TX(US);Austin TX(US);Austin TX(US)
  • 作者单位

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-20-1 Josuihoncho, Kodairashi, Tokyo, 187, Japan;

    Semiconductor Integrated Circuits Div., Hitachi, Ltd. 5-;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 半导体器件制造工艺及设备;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号