Chip Speed Prediction Model for Optimization of Semiconductor Manufacturing Process Using Neural Networks and Statistical Methods

摘要

As the increase of device complexity, prediction of chip performance such as chip speed is crucial as much as yield prediction model in semiconductor manufacturing. In this paper, hybrid of circuit simulation and DOE (design of experiment) are applied to develop speed prediction models for high-speed microprocessor manufacturing process. Speed prediction models are developed through three steps; transistor ratio variation analysis step, electrical test data analysis step, and fabrication test data analysis step. Artificial neural networks are used to find relation between measured data and chip speed and network inputs are selected based on statistical analysis. Electrical test based modeling results showed only 1.2% of RMS error and fabrication level speed prediction model showed 83% of fitness results.