Exploring multiple levels of parallelism using BOPS' DSP

摘要

A study of high performance, reusable and scalable DSP architecture of BOPS, which targets specific applications, is carried out. The degree of parallelism supported by the BOPS' ManArray architecture and its usability is tested on various algorithmic building blocks along with the more complex and irregular algorithm of the G.729a vocoder, a key requirement of VoIP gateway DSP engine. An analysis to reduce complexity as well as implementation of G.729a on an array processor using various optimization techniques is presented.