A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power Converters

摘要

We present a Smart Power ASIC (SPIC) for a cascaded power converter. The distributed power system comprises a power-factor-correction circuit (PFC) followed by a full-bridge zero-voltage-switched converter (FB-ZVS). The SPIC is capable of driving three low-side and two high-side power devices. Integration of the current-mode and the voltage-mode controllers for the PFC and the FB-ZVS, respectively, along with the driver and the fault-protection circuits for the two-stage power converter are implemented on a single ASIC. The integrated circuit incorporates fault-protection features such as under-voltage lockout, over-current protection, adaptive shoot-through protection, and soft-start capability. A combination of bootstrap and charge-pump techniques is used to power the gate-drive circuit for the high-side power devices. Therefore, the SPIC is capable of achieving a 100% duty cycle. The SPIC is implemented in Cadence, using a 0.5 μ mixed-signal CMOS technology. A 500 W power converter is designed and simulated in Saber Designer 2001.4. Subsequently, a complete system-level simulation is performed using the Cadence Frame-way Integration Technology (in Native Simulation mode), which enables the integration of the power stage and SPIC models developed in Saber Designer and Cadence, respectively. The SPIC leads to higher power density, reduced design-cycle time, enhanced reliability of the overall switching power system due to integration of drivers and controls, and a more effective two-stage fault-protection scheme.