High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card

摘要

This paper discusses a design method of Rijndael coprocessor for USIM card. It requires small area, law power, and reasonable data processing speed. Ours coprocessor performs round operation by 64 bits instead of 128 bits. So we can obtain small area. And some hardware design techniques are employed to save hardware resource and increase performance. The design is described using VHDL and synthesized by Synopsys with 0.25 um CMOS fabrication. And it is simulated using ModelSim and tested using FPGA card emulator board. Results show that with a design of 19K gates.