An Improved BIST Testability-Metrics Based High-Level Test Synthesis Approach

摘要

In this paper, we describe a Built-in Self-Test syn-thesis approach for integrating operation scheduling and data path allocation. In our previous work, we presented a synthesis algorithm based on BIST testability-metrics at register-transfer level. In our present approach, with the help of an incremental BIST testability analysis and a state reachability analysis with its incremental approach for control path at register-transfer level, we mainly make use of some concepts and techniques to improve the previous work not only during the data path synthesis part, but also during the operation scheduling part. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.