Optimizing Power Using Advanced Voltage Scaling Techniques in Logic Synthesis

摘要

Dual supply voltage scaling (DSVS) and dual threshold voltage scaling (DTVS) are versatile techniques for reducing dynamic and static power consumption of CMOS circuits. In contrast to other advanced voltage scaling techniques, DSVS and DTVS can both be automated in logic synthesis, which minimizes the design effort. While this is straight forward for DTVS, special care must be taken regarding level conversion and power modeling in the case of DSVS. We developed the first methodology for delay-constrained optimization of dynamic power through DSVS in a near-standard logic synthesis environment. We applied this methodology to various MCNC benchmark circuits and observed up to 20% improvement in power consumption over state-of-the-art power-driven logic synthesis. Our methodology can easily be transformed into a hybrid DSVS-DTVS methodology for delay-constrained optimization of dynamic and static power.