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ISOLATING ANALOG CIRCUITS FROM DIGITAL INTERFERENCES

机译:从数字干扰中隔离模拟电路

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Recent advances in analog integrated circuit techniques and continued improvement in VLSI technology are enabling more and more mixed-signal analog digital integrated circuits to be implemented on the same chip. One of the important recent topics in mixed signal circuit design, is the coupling of digital switching noise onto sensitive nodes in the analog circuits [1,3]. Traditionally, guard rings formed by substrate contacts have been used to prevent such crosstalk, as illustrated in Fig.1a. As the substrate is lightly doped, noise coupled from the digital circuit, such as that through the pn junction of the drain of an inverter, tends to travel to the analog part of the circuit along the surface, which can be easily intercepted by guard rings formed by p~+ diffusion. In modern technologies, however, the substrate usually starts with a heavily doped p~+ layer several hundred microns thick, followed by a thin p~- epi layer on which circuits are formed. This is illustrated in Fig.lb. While this kind of process is much less susceptible to latch-up, the guard ring method for isolating analog from digital circuits is no longer effective. As the substrate resistance between any two point in the p~+ layer is only a few ohms, the shortest resistive path between any two points near the surface of the epi-layer is no longer along the surface but rather first vertically down to the heavily doped p~+ layer, through it and then vertically back up to the second point on the surface. The vertical paths down to the p~+ layer also have low resistance because of the large average cross section of the path as compared to the vertical distance.
机译:模拟集成电路技术的最新进展以及VLSI技术的不断改进,使得越来越多的混合信号模拟数字集成电路可以在同一芯片上实现。混合信号电路设计中最近的重要课题之一是将数字开关噪声耦合到模拟电路的敏感节点上[1,3]。传统上,如图1a所示,已使用由基板触点形成的保护环来防止这种串扰。当轻掺杂衬底时,从数字电路耦合的噪声(例如通过反相器漏极的pn结的噪声)趋于沿着表面传播到电路的模拟部分,很容易被保护环拦截由p〜+扩散形成。然而,在现代技术中,衬底通常以几百微米厚的重掺杂p- +层开始,然后是在其上形成电路的薄p-- Epi层。这在图1b中示出。尽管这种处理不太容易发生闩锁,但用于将模拟电路与数字电路隔离的保护环方法不再有效。由于p〜+层中任意两点之间的衬底电阻仅为几欧姆,因此外延层表面附近任意两点之间的最短电阻路径不再沿着表面,而是首先垂直向下直至重掺杂p〜+层,穿过它,然后垂直回到表面上的第二个点。垂直至p〜+层的垂直路径的电阻也较低,因为与垂直距离相比,该路径的平均横截面较大。

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