Quaternary Arithmetic Logic Unit on a Programmable Logic Device

摘要

Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) cany propagation delay where n is the number of digits. Carry lookahead helps to improve the propagation delay to O(log n), but is bounded to a small number of digits due to the complexity of the circuit. A carry-free arithmetic operation can be achieved using a higher radix number system such as Quarternary Signed Digit (QSD). In QSD, each digit can be represented by a number from -3 to 3. This number system allows multiple representations of any integer. By exploiting this feature, we can design an adder without ripple carry. The implementation of quarternary addition and multiplication results in a fix delay independent of the number of digits. Operations on a large number of digits such as 64, 128, or more, can be implemented with constant delay and less complexity. This paper focuses on the implementation of quarternary addition and multiplication. Results are verified and the performance is shown to be consistent with the constant delay model.