An Interface Methodology for Retargettable FPGA Peripherals

摘要

Initially, IP cores in System-On-Chip (SOC) were interconnected through custom interface logics. The more recent use of standard on-chip buses has eased integration and eliminated inefficient glue logic, and hence boosted the production of IP functional cores. However, once an IP block is designed to target a particular on-chip bus standard, retargeting to a different bus is time consuming and tedious. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Industry standard Bus Wrappers are intended to ease the interface problem, but performance overheads make them unattractive. A new methodology is presented that can automate the connection of an IP block to a wide variety of interface architectures with low overhead through the use a special Interface Adaper Logic layer.