A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme

摘要

A hybrid wave-pipeline multiplier architecture is described in this paper. Mathematical analysis is provided to show the performance gains possible with hybrid wave-pipeline over conventional pipeline architectures. The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8 x 8-bit hybrid wave-pipeline multiplier using carry-save adder technique is fully described. The multiplier has been designed using TSMC 180nm (drawn length 200nm). Since in hybrid wave-pipelining clock period is proportional to delay difference, short clock periods can be obtained by minimizing the delay difference. The basic cells in multiplier are designed to have small propagation delay and delay variation. The pipelined multiplier is able to achieve 2.86 billion multiplications per second. The delay balancing necessary to reduce the delay variation is simpler in hybrid wave-pipeline architecture than in wave-pipeline architecture.