Design for Test Methodology for the IBM PowerPC™ 440 Embedded Core

摘要

This paper presents a Design-for-Test (DFT) methodology for the IBM PowerPC™ 440 embedded processors implemented in 130 nm technology. The paper discusses highlights of the DFT techniques that address challenges of achieving highly testable and debuggable product. The paper addresses enhancements of debugging by providing better tracking of initial silicon capabilities for improved yield and time-to-market.