Test methodologies and design automation for IBM ASICs

摘要

IBM manufactures a very large number of different application-specific integrated circuit (ASIC) chips each year. Although these chips are designed by many different customers having various levels of test experience and all having tight deadlines, IBM ASICs have a reputation for their high quality. This quality is due in large part to the heavy focus on design for test (DFT) and the use of design automation to help ensure that customers'' chips can be manufactured, tested, and diagnosed with minimal engineering effort. Prospective customers of IBM ASIC technologies find an explicit set of DFT methodologies to follow which provide a relatively painless, almost push-button approach to the generation of high-quality, “sign-off” test vectors for their chips. This paper discusses the DFT methodologies used for IBM ASICs and the design automation support that enables designers to be so productive with these methodologies. Data are given for several recently processed chips, some designed outside IBM.