Compact Linear Systolic Arrays for Multiplication Using a Trinomial Basis in GF(2~m) for High Speed Cryptographic Processors

摘要

Many of the cryptographic schemes over small characteristic finite fields are efficiently implemented by using a trinomial basis. In this paper, we present new linear systolic arrays for multiplication in GF(2~m) for cryptographic applications using irreducible trinomials x~m + x~k + 1. It is shown that our multipliers with trinomial basis require approximately 20 percent reduced hardware resources compared to previously proposed linear systolic multipliers using general irreducible polynomials. The proposed linear systolic arrays have the features of regularity and modularity, therefore, they are well suited to VLSI implementations.