VLSI Design of Bit-Retimed and Pipelined Digital Recursive Filters

摘要

This paper suggests a bit-level retime and pipelining (BRP) technique that improves the area-time-power performance of digital recursive filters. The technique is based on the fast bit-retiming technique proposed earlier. The example shows that BRP based filter is 44% smaller. 22% faster and consumes 12% less power than a non-retimed equivalent.