Wafer thinning and planarization technology for 3D Interconnects

摘要

Making reliable through-die interconnects requires development of deep via technologies, as well as thinning and stacking technologies. This type of integration puts forward new challenges and additional constraints, all influencing performance and cost. One of the options to 3D integration pursued at IMEC, is the stacked IC approach (3D-SIC). Before stacking a copper via containing chips onto the next one, they need to be drastically thinned to below 100 μm. The thinning is performed on a full wafer. In this thickness range, wafers cannot be individually handled and therefore they must be mounted on a carrier wafer before thinning. This thinning is subsequently done by a combination of grinding and CMP. In this paper we will address the thinning module of this integration route.