On-chip memory is a major design issue in current chip multiprocessors (CMPs) due to performance and power reasons. Internal memory is typically composed of many structures both private (at least LI ICache and LI DCache per core) and shared (e.g. LLC caches) and must be properly organized to mitigate the huge latencies of accessing off-chip DRAM memory. These memory structures must be smartly interconnected to avoid performance penalties. In addition, on-chip memory occupies by two thirds of the processor area, thus performance must be achieved with reasonable power consumption. Moreover most designs must be tailored to meet a given power budget. These design issues become more important with the increasing core counts in future microprocessor generations.
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