Memory FIT Rate Mitigation Technique for Automotive SoCs

摘要

This paper considers the reliability and safety issues in automotive applications which are of highest importance. FIT rate is one of the most common metrics used for quantitatively evaluating such issues. Strict requirements exist for acceptable FIT Rate in automotive applications. The problem of calculating the FIT rate at SoC level is considered in this paper and then it focuses on memories, which comprise a large part of current SoCs and have a great impact on the overall FIT rate. The vulnerability factors are considered, which help to get a better approximation of real-life situations. A methodology is presented for mitigating the effects of soft errors in memories via selective adoption of error detecting and correcting codes (ECC). Ways to calculate the FIT rate in the presence of ECC are considered and an advanced ECC solution is presented. Since using ECC increases the SoC area (extra logic and memory bits are needed) and decreases performance (delay in ECC logic that calculates / verifies the codes), a planning solution for choosing which memories should have ECC for optimal reliability/area is presented. Some experimental results are adduced to illustrate the effectiveness of the proposed techniques.