Stochastic LUT-based reliability-aware design method for operation point dependent CMOS circuits

摘要

In this paper a Reliability-AwaRE (RARE) method based on the gm/ID-methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. The proposed method makes aging simulations on system level superfluous by utilizing a stochastic Look-Up table. The stochastic LUT contains simulated data from single NMOS and PMOS devices describing their small signal characteristics. Subsequently circuit performances can be predicted. Exemplarily, a reliability-aware design for common source amplifiers is shown and the predicted values are compared to those from a traditional simulation showing good data fitting and small deviations.