A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator for Low-Voltage Applications

摘要

This paper presents an energy-efficient low-voltage double-tail dynamic latch comparator which shows high switching speed in comparison to conventional design. The proposed comparator is designed using improved pre-amplifier stage in which hybrid design style is adopted to enhance latch speed with optimum power. As a result, energy efficiency is improved. The analytical expressions for delay calculation are also derived for the proposed comparator. The rigorous simulations are analyzed in CADENCE SPECTRE at 90nm CMOS technology with 1V power supply. The mismatch analysis for offset voltage is validated using Monte-Carlo simulations at 200 samples. The simulations and analytical derivations corroborate that the enhanced speed is achieved with low-offset and optimized power dissipation. The simulation results confirm that the proposed design is about 2 times faster, 52.89% more energy efficient, and minimizes 27.51% offset voltage in contrast of conventional dynamic comparator at the cost of 20.39μW power consumption and 54.03μm