Self-timed techniques for low-power digital arithmetic in GaAs VLSI

摘要

This article presents a self-timed approach to digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems. The design techniques are based on GaAs Latch-Coupled FET Logic (LCFL) in order to achieve reasonable power-delay-area trade-off. The complexities due to clock skew are avoided and power savings schieved through the pipelined architecture. A range of arithmetic circuits is presented and their perfomance evaluated.