Iterative ring and power-aware design techniques for self-timed digital circuits.

摘要

Asynchronous design has received a revival of interest recently, because it promises to avoid overhead due to clock skew, worst-case design assumptions and resynchronization of asynchronous external inputs. NULL Convention Logic (NCL) has been introduced as an asynchronous design employing dual-rail signals to incorporate data and control information into one mixed path. However, since NCL is still conceptually young, there is no current formal methodology for designing and analyzing NCL circuits. This main contributions of this dissertation include: (1) A synthesis method for simple NCL combinational circuits has been developed. This method achieves optimized designs for some circuits in terms of area, and inherently avoids gate orphans that are delay-sensitive. (2) By applying dependency graph to analysis of NCL rings, some important principles for ring design have been obtained. These principles will be used as guidelines to optimize the design of a 24-bit division. (3) Supply voltage scalable system design for NCL low power has been investigated. Two architectures are proposed to achieve supply voltage scalability, for preserved quality and energy-quality tradeoff respectively, In the fist architecture, the supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement and processing quality. In the second one, further energy saving is achieved at the cost of signal-noise-ratio loss in digital signal processing when an ultra-low supply voltage is applied. (4) Based on NCL handshaking protocol, a globally asynchronous locally synchronous system is proposed. This work paves the way for more feasible applications of NCL.