RF interface design using mixed mode methodology

摘要

A VHDL-SPICE mixed-signal modeling methodology is applied to the RF interface of A DECT ASIC designed in CMOS 0l.35 #mu# m technology. An overview of actual mixed design flows is presented followed by the DECT system description. Then a mixed-signal methodology is introduced to validate the whole circuit behavior. We illustrate the approach with detailed models, simulation resul;ts and experimental data. The chip was successfully tested and produced by VLSI Technology.