An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

摘要

An all-digital switched-capacitor (SC) based clock frequency (Felk) and supply voltage (V dd) regulator unifies Fclk and Vdd generation into a single control loop to reduce the V dd margin for variations in a sub-threshold ARM Cortex M0 processor. This fully-integrated unified clock and power (Uni-CaP) architecture allows continuous Vdd scalability without a low-dropout (LDO) regulator. Measurements from a 65nm test chip demonstrate a 16% Vdd reduction (94% Vdd margin recovery) and a 3.2× increase in Fclk operating range.