首页> 外文会议>2019 IEEE International Conference on Artificial Intelligence Circuits and Systems >A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices
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A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices

机译:具有CNN-FFT加速器的2.17mW声学DSP处理器,用于智能助听器

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This paper proposes an acoustic DSP processor with a neural network core for speech enhancement. Accelerators for convolutional neural network (CNN) and fast Fourier transform (FFT) are embedded. The CNN-based speech enhancement algorithm takes the speech signals spectrogram as the model's input, and predicts the desired mask of speech to enhance speech intelligibility after passing through the CNN model. An array of multiply-accumulator (MAC) and coordinate rotation digital computer (CORDIC) engines are deployed to efficiently compute linear and nonlinear functions. Hardware sharing is applied to reduce hardware area by leveraging the high similarity between CNN and FFT computations. The proposed DSP processor chip is fabricated in a 40-nm CMOS technology with a core area of 4.3 mm2. The chip's power dissipation is 2.17 mW at an operating frequency of 5 MHz. The CNN accelerator supports both convolutional and fully-connected layers and achieves an energy efficiency of 1200-to-2180 GOPS/W, despite the flexibility for FFT. The speech intelligibility can be enhanced by up to 41% under low SNR conditions.
机译:本文提出了一种具有神经网络核心的声学DSP处理器,用于语音增强。嵌入了用于卷积神经网络(CNN)和快速傅立叶变换(FFT)的加速器。基于CNN的语音增强算法将语音信号频谱图作为模型的输入,并预测所需的语音掩码,以增强通过CNN模型后的语音清晰度。部署了一系列乘累加(MAC)和坐标旋转数字计算机(CORDIC)引擎来有效地计算线性和非线性函数。通过利用CNN和FFT计算之间的高度相似性,可以应用硬件共享来减少硬件面积。所提出的DSP处理器芯片是采用40纳米CMOS技术制造的,其核心面积为4.3毫米\ n <=>“ http://www.w3.org/1998/Math/MathML \” xmlns: xlink = \“ http://www.w3.org/1999/xlink \”> 2 \ n。在5 MHz的工作频率下,该芯片的功耗为2.17 mW。 CNN加速器支持卷积层和完全连接层,并且尽管FFT具有灵活性,但仍能达到1200至2180 GOPS / W的能效。在低SNR条件下,语音清晰度可提高多达41%。

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