A real time FFT chip set: architectural issues

摘要

The tradeoffs involved in the design of a real-time 40-MHz fastFourier transform (FFT) chip set are discussed. Tradeoffs involving thealgorithmic organization, device partitioning, the data format, anddevice architecture are examined. The chip set can compute FFTs with upto 2048 points at 40-MHz data rates (or 80-MHz data rates for real data)by using up to 20 chips or at 3-MHz rates when using only three devices.The 1.5-μ CMOS chip set has been designed, fabricated, and tested andis fully functional