A low latency simultaneous quantization Vernier delay-line-based ADC for digital control single-inductor-multiple-output DC-DC converter

摘要

A low latency Vernier delay-line-based window ADC capable of simultaneous quantization for digital control single-inductor-multiple-output (SIMO) DC-DC converter is proposed in this work. The ADC converts signals of feedback voltages and sensed inductor current by voltage-time converter (VTC) and successive time-digital converter (TDC). Together with a subrange quantization scheme, a preceding interleaving Vernier delay line method is proposed in the TDC, which offers 7bits resolution for each channel and makes the latency of A/D conversion lower than 5ns. Moreover, benefited from the TDC architecture, MSB and LSB time references generated by delay line are shared with all channels, which reduce the amounts of delay line as well as matching difficulty and power consumption. As a result, it is suitable for the application requiring multiple channels and low conversion latency. The proposed ADC is designed in 0.18μm CMOS process and provides 6 quantization channels for a digital control SIMO DC-DC converter which regulates four output voltages to 1.8V, 2.5V, 3.3V and 5V individually.