Design of a Low-power Single-channel 8-Bit 1.25GSPS SAR ADC

摘要

Successive approximation register analog to digital converter (SAR ADC) has incomparable energy efficiency advantages over other types of ADC architectures for its high degree of digitalization and simple structure. Undergoing algorithm verification with MATLAB, a single-channel 8-bit 1.25GSPS SAR ADC structure is presented. Transistors level circuit has been designed using TSMC 28nm CMOS technology. The pre-simulation results with noise show that the core circuit has the ENOB 7.80bits, the power consumption 2.01mW, and the FOM value 6.29fJ/conv-step when operating at very high speed with sampling rate of 1.25GSPS under 1.2V supply.