Department of Electronics Communication Engineering, Dr. B. C. Roy Engineering College, Durgapur, India;
Department of Electronics Communication Engineering, Dr. B. C. Roy Engineering College, Durgapur, India;
Department of Electronics Communication Engineering, Dr. B. C. Roy Engineering College, Durgapur, India;
Department of Electronics Communication Engineering, Dr. B. C. Roy Engineering College, Durgapur, India;
Department of Electronics Communication Engineering, Dr. B. C. Roy Engineering College, Durgapur, India;
MOS devices; Multivalued logic; Logic gates; Integrated circuit modeling; CMOS technology; Delays; Semiconductor device modeling;
机译:基于DPL的三元逻辑电路的系统设计策略
机译:基于三元决策图(TDD)的三元逻辑电路综合方法
机译:基于三元逻辑电路的三元决策图(TDD)合成方法
机译:设计DPL的三元逻辑电路的新方法
机译:平衡延迟不敏感的三元逻辑电路,用于缓解侧通道攻击
机译:一种使用QCA实现具有成本效益的算术逻辑电路的新型可逆逻辑门及其系统方法
机译:使用GNRFET设计三元逻辑和算术电路