Implementation and performance analysis of variable latency adders

摘要

Asynchronous circuit design is enjoying resurgence in the digital world, with many recent technical and practical advancements and improvements. The advantages of asynchronous systems over synchronous systems are promising. The opportunity to implement high performance data-paths is very attractive by exploiting the fact that most data-path modules have data dependent delays. In other words they compute the result faster than worst case under many input combinations. Therefore making the common case fast, asynchronous data-paths have the potential to outperform synchronous designs on average inputs. This paper is devoted to the implementation and analysis of the performance advantages that can be achieved by dynamically selecting the matched delay in a bundled-data setting. It presents the implementation and analysis of a method for the design of high performance asynchronous adders called “speculative completion” on six different 32 bit adders. The analysis on random data indicates that speculative completion yields significant performance improvements. It is also noticed that the performance improves further in case of small number additions. On average, the 32-bit Brent Kung speculative adder is 19.4% faster than a 32-bit Brent Kung without speculative completion if both inputs are 32 bits and 24.8% faster if both inputs have only 16 non zero bits. Similarly Kogge Stone and Sparse Tree adders are 24.2% faster; Ladner Fischer, Han Carlson and Sklansky are 16 %, 22.75% and 18.5 % faster respectively.