Using Both VHDL and Verilog for Board-Level Simulation

摘要

Acuson designs and manufactures highend medical ultrasonic imaging machines. Like many companies in Silicon Valley, it has traditionally been a verilog house. Verilog was originally used for ASIC design and verification. More recently, it has been used for FPGA synthesis. It has worked fine in these applications. We intend to continue using it as a front end to synthesis and as a signoff simulator for ASIC vendors. Eventually Verilog found its way into boardlevel simulations. Here difficulties were encountered. The first problem was in netlisting. Because Verilog is used primarily for chip design where a single library is used, the netlister did not handle multiple libraries well and was famous for spewing out error messages that were totally unrelated to the actual errors.