A kind of All Digital Phase-Locked Loop Implemented with Erasable Programmable Logic Devices

摘要

This paper discusses a kind of ADPLL (All Digital Phase-Locked Loop) implemented with Altera's EPLD , which is used as the bit synchronization circuit in communication system. EPLD's in-system programmability (ISP) makes this kind of ADPLL more flexible. The paper introduces the design thought and implementation procedure of the ADPLL and evaluates its performance.