A System Level Teaching Environment for Designing the 32 Bit DLX Microprocessor

摘要

At University Pierre et Marie Curie, there is an advanced course on VLSI design training which is based on the design and implementation of the DLX 32 bit micro-processor specified by Hennessy and Patterson with the public domain ALLIANCE CAD system. Many of the verifications steps throughout the design flow are based on logical simulation. Such a verification can rapidly become very time consuming. Here we present the simulation method that we have defined. It makes the simulation steps as transparent as possible to the designers, reducing the critical path in the debugging loop. The idea is to reduce the amount of information needed for a simulation session. This is done by performing simulation at a system level instead of the processor level. An entire CPU board has been described in VHDL including the DLX, an address decoder, RAMs, ROMs and a timer for external interrupts. Checking the correctness of the processor consists in writing a sequence of instructions and running it on the CPU board.