A PURE CORDIC BASED FFT FOR RECONFIGURABLE DIGITAL SIGNAL PROCESSING

摘要

This paper presents a pure Cordic based architecture to calculate the FFT on a reconfigurable hardware accelerator. The performance of this approach can compete with the ordinary MAC based implementation on this accelerator, although the main advantage is the possibility to implement the FFT on a reconfigurable Cordic-only processor array. In a former publication it was already shown that the Rake receiver can be replaced by a Cordic based linear equalizer using the same architecture, which even results in a better performance. With the presented pure Cordic based FFT it is now possible to replace the main processing blocks of the WLAN and UMTS baseband by this programmable architecture.