Boundary-Scan Interconnect Test Vector Generation During VHDL Synthesis

摘要

In this paper we present a group of VHDL functions that generate the interconnection test vectors for a boundary-scan board. The functions are part of a synthesizable VHDL model for a boundary-scan chain, to be received from it, and to enable the evaluation of the received response. The information needed by these functions are the boundary-scan data of the components of the board and a description of the interconnections between the cells. Using these functions the synthesis tool generates the vectors without needing any other external Automatic-Test-Pattern-Generation (ATPG) program.