New Aspects in HDL''s Performance Evaluation

摘要

New aspects in Hardware Description Language''s (HDL) performance evaluation such as object-orientation, system-level modeling, analog and mixed-signal modeling, software description and verification capabilities are analyzed in this paper. Features of mainstream HDLs and verification languages VHDL-AMS, Java, SystemC, AleC++, MLDesigner, OpenVera, the e language, PSL and System Verilog are compared in the context of these aspects.