COMPLIANT STRESS-ENGINEERED INTERCONNECTS FOR-NEXT GENERATION PACKAGING

摘要

Future demands of microelectronic packing include increasing input/output (I/O) densities, providing high frequency capabilities, and maintaining sufficient reliability while keeping costs minimal. Organic materials with Coefficients of Thermal Expansions (CTE) over four times greater than silicon will continue to be used as future substrate materials because of their low cost. Consistent with the International Technology Roadmap for Semiconductors (ITRS, 2003), chip-to-substrate interconnects will need to have a pitch approximately equal to 40μm by the year 2012 and be able to accommodate the silicon and organic CTE mismatch without resorting to expensive reliability solutions. The demand for fine pitch chip-to-substrate interconnects combined with the CTE mismatch, creates significant demands for overall interconnect compliance as means to ensure reliability, through increasing fatigue life. Stress-engineered compliant off-chip interconnects are capable meeting future interconnect demands. Such interconnects are fabricated from stress-engineered metal thin-films using traditional IC fabrication methods and can be integrated with wafer level packing. A systematic design approach has been used to optimize interconnect geometry for use with estimated operational conditions. Finite Element Analysis (FEA) and Regression modeling have been used to create macro-models of interconnect behavior to assist in the optimization of the geometric design. Copper and Copper-Molybdenum are considered as interconnect material and the development intrinsic stress within copper is investigated via sputter deposition.