B. P. Poddar Institute of Management and Technology, 137, VIP Road, Kol 700052, India;
B. P. Poddar Institute of Management and Technology, 137, VIP Road, Kol 700052, India,Department of Engineering and Technological Studies, Kalyani University, Kalyani 741235 West Bengal, India;
Department of Computer Science and Engineering, West Bengal University of Technology, BF-142, Sector-Ⅰ, Salt Lake City, Kolkata 700064, India,School of Physics, University of Western Australia, M013, 35 Stirling Highway, Crawley, Perth WA 6009, Australia;
Department of Engineering and Technological Studies, Kalyani University, Kalyani 741235 West Bengal, India;
Parity preserving; Conservative logic gate; Reversible logic gate; 5-input majority voter; Online testing;
机译:具有故障安全逻辑的量子点元胞自动机中可测试加法器的设计
机译:基于节能紧凑的二维二维两点单电子量子点细胞自动机的脉动进位加法器的设计与分析
机译:在量子点元胞自动机电路的新型“多层门设计范例”中使用5输入多数门进行加法器设计
机译:量子点蜂窝自动机的在线可测量保守加法器设计
机译:量子点元胞自动机中的64位面积有效二进制加法器。
机译:量子点元胞自动机中高效全加器的设计
机译:基于量子点蜂窝自动机技术的4位纹波携带加法器的新共面设计