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Impedance of power distribution networks in TSV-based 3D-ICs

机译:基于TSV的3D-IC中配电网络的阻抗

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To estimate the simultaneous switching noise (SSN) on the three dimensional VDDQ power distribution network (3D VDDQ PDN) in a TSV-based GPU system, the PDN impedance (ZPDN) and the pull up impedance (Zpull-up) of the VDDQ PDN in the GPU system were first estimated and analyzed. The GPU system consisted of a GPU, quadruple-stacked DRAMs, a silicon interposer and an organic package. The impedance estimation method, based on a segmentation method and a balanced-transmission line method (Balanced-TLM), was used for the estimation of the PDN impedance and the pull-up impedance of the 3D VDDQ PDN, combining the models of the chip PDNs, S/G lines, P/G TSV pairs, and a package PDN. The PDN impedance and the pull up impedance were also analysed with respect to the variation in the number of the P/G TSV.
机译:为了估算基于TSV的GPU系统中的三维VDDQ配电网络(3D VDDQ PDN)上的同时开关噪声(SSN),VDDQ PDN的PDN阻抗(ZPDN)和上拉阻抗(Zpull-up)首先对GPU系统中的数据进行了估算和分析。 GPU系统由GPU,四重DRAM,硅中介层和有机封装组成。基于分段方法和平衡传输线方法(Balanced-TLM)的阻抗估计方法结合了芯片模型,用于估计3D VDDQ PDN的PDN阻抗和上拉阻抗PDN,S / G线路,P / G TSV对和程序包PDN。还针对P / G TSV数量的变化分析了PDN阻抗和上拉阻抗。

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