We recently explored the concept of using BER-optimal ADCs for high-speed links. In this paper, we study the benefits of BER-optimal ADCs in terms of power savings and relaxation of component specifications in a 90 nm 1.2V CMOS process. These analyses are based on component models for a flash ADC that capture bandwidth limitation of pre-amplifiers and metastability of latches. We show that in the presence of these ADC non-idealities, a 3-bit BER-optimal ADC can provide a 3 dB ADC shaping gain over a 4-bit conventional ADC. The one bit reduction offers power savings of 75% in the VGA and 50% in the ADC. Further, the 3dB ADC shaping gain can be traded-off for a 50% reduction of transmit driver power, a 75% reduction of the pre-amplifier bandwidth, or a saving of one latch stage that leads to a 20% additional power reduction in the ADC.
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机译：我们最近探讨了将BER最佳ADC用于高速链路的概念。在本文中，我们研究了90nm 1.2V CMOS工艺中的BER最佳ADC在节省功率和放松组件规格方面的优势。这些分析基于闪存ADC的组件模型，该模型捕获了前置放大器的带宽限制和锁存器的亚稳性。我们表明，在存在这些ADC非理想性的情况下，3位BER最佳ADC可以比4位常规ADC提供3 dB ADC整形增益。减少一位可在VGA中节省75％的功耗，在ADC中节省50％的功耗。此外，可在3dB ADC整形增益之间进行权衡，以降低50％的发射驱动器功率，75％的前置放大器带宽或节省一个锁存级，从而使功耗降低20％。 ADC。
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