Optimized TSV process using bottom-up electroplating without wafer cracks

摘要

In this paper, we propose the bottom-up electroplating without the additional process to resize the wafer for the fabricating the TSVs. It is also able to be the good solution for the wafer crack because of the vertical shape at the wafer edge after wafer thinning. The TSV process using bottom-up electroplating consists with DRIE, deposition of isolation and barrier layers, Au-to-dielectric bonding of wafers, wafer thinning, Cu electroplating and removing the carrier wafer. The DRIE process is not defining outline of the resizing area but also forming the vias on the wafer. After wafer bonding, the outer of the outline is removed through the thinning process and then the wafer size is reduced without the additional cutting process. The edge of the resized and thinned wafer with the vias has the vertical shape like the DRIE profile. The fabricated TSVs have the diameters of 10, 60, and 120 um. Thicknesses of the wafers with the TSVs are 50, 100, and 200 um. From SEM and 3D X-ray analysis, any defect is not observed in the TSVs. The TSV wafers are sawed without the cracks and separated to individual chips with the area of 7 mm × 7 mm. To stack the chips using flip-chip bonding, bumps on the chips are made on the TSVs by using the solder bump maker (SBM) made of a resin and solder powder of Sn58Bi. These can reduce the process cost. The functions of resin and the solders in the SBM are flux removing oxide layer and raw material of the bumps, respectively. The chips are stacked by using flip-chip bonding and solder bumps on the TSVs.