Department of Electronics and Communication Engineering, Silicon Institute of Technology, Bhubaneswar;
Department of Electronics and Communication Engineering, Silicon Institute of Technology, Bhubaneswar;
Department of Electronics and Instrumentation Engineering, Silicon Institute of Technology, Bhubaneswar;
Department of Electronics and Instrumentation Engineering, Silicon Institute of Technology, Bhubaneswar;
School of Electronics Engineering, Vellore Institute of Technology, Amaravati;
Department of Electronics and Communication Engineering, Silicon Institute of Technology, Bhubaneswar;
Department of Electronics and Instrumentation Engineering, Silicon Institute of Technology, Bhubaneswar;
Logic gates; MOSFET; High-k dielectric materials; Permittivity; Transconductance; Capacitance; Performance evaluation;
机译:具有栅堆叠结构的对称下叠DG-MOSFET的高k隔离层分析
机译:高k隔层非对称下叠DG-MOSFET的谐波失真分析
机译:外延LU或Y掺杂LA2O3 / LA2O3 / GE高k门堆的电气性能
机译:高k垫片对栅极堆均匀掺杂DG-MOSFET的影响
机译:纳米级处理中的等离子体表面相互作用:通过硅选择性保留低k完整性和高k栅堆叠蚀刻。
机译:高性能锂离子电池中富含锂和锰的阴极中均匀的Na +掺杂诱发的缺陷
机译:用非弹性方法调整Gaas基太阳能电池的性能 散射量子点和掺杂alyGa1-ysb型-II点和 点之间的alxGa1-xas间隔物
机译:均匀掺杂和高低掺杂肖特基ImpaTT的有源区内的瞬态温度分布。