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Effect of High-K Spacer on the Performance of Gate-Stack Uniformly doped DG-MOSFET

机译:高K隔离层对栅堆叠均匀掺杂DG-MOSFET性能的影响

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In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO2 and the other as high-K i.e- HfO2. Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.
机译:在这项工作中,我们分析了栅极叠层双栅极(DG)MOSFET关于不同间隔物变化的新颖性,以减少短沟道效应的挑战并同时提高器件性能。硅与栅极堆叠技术一起用作沟道材料,用于研究器件的模拟性能和射频(RF)性能。对于栅堆叠,使用两种类型的氧化物-一种表示低K,即SiO \ n 2\n,另一个为高K,即HfO \ n 2 \ n。使用具有不同介电常数的垫片来了解其对设备性能的影响。仿真结果表明,隔离材料的使用对器件的模拟和RF行为都有很大影响。 SILVACO International已进行了计算机辅助设计(TCAD)模拟。

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